1. Field of the Invention
This invention relates to artifical cardiac pacemakers, either external or implantable having a sense amplifier for sensing natural heart signals.
2. Description of the Prior Art
The implantable cardiac pacemaker, shown in U.S. Pat. No. 3,057,356 and subsequent patents permits innocuous, painless, long-term cardiac stimulation at low power levels by utilizing a small completely implanted transistorized and battery operated pulse generator connected via a flexible lead bearing an electrode directly in contact with cardiac tissue. Most pulse generators consist of a stimulating circuit and a sensing circuit both of which draw current from the battery. In the presence of complete heart block, an asynchronous pulse generator with only a stimulating circuit may be used, however, in most instances, noncompetitive triggered or inhibited pulse generators having the sensing circuit are preferred and dominate the pacemaker market. The demand, synchronous or triggered pulse generators are especially useful in patients with spontaneous cardiac activity because of their ability to sense intrinsic cardiac rhythm (atrial or ventricular depending on variety and electrode position), and to alter the pacemaker output accordingly. Such pacemakers are shown for example, in U.S. Pat. Nos. 3,253,596 (P-wave synchronous), 3,478,746 (ventricular inhibited) and are described in the pacing literature.
More recently, attention has been paid to the physiological aspects of cardiac pacing therapy and particularly to pacing systems for maintaining synchronous atrial and ventricular depolarization of the heart. In early atrial synchronized (or A-V synchronous) pacing, atrial depolarization is sensed through one electrode, and after an appropriate delay the ventricle is paced through a different electrode, thereby restoring the normal sequence of atrial and ventricular contraction and allowing the pacer to respond to physiologic needs by increasing its rate. Below a predetermined minimal atrial rate, however, the pacemaker reverts to its basic ventricular pacing rate. In atrial synchronous, ventricular inhibited pacers of the type described in U.S. Pat. Nos. 4,059,116 and 3,648,707, the ventricular depolarizations are also sensed and inhibit or reset the timing of the ventricular stimulating pulse generator.
A more complex method of restoring synchrony is by the atrial ventricular sequential pacing of the type described in U.S. Pat. No. 3,595,242 and subsequent patents which possess atrial and ventricular pulse generators and associated electrodes and a ventricular sensing circuit. In atrial ventricular sequential pacing, the atria and ventricles are paced in proper sequence, the atrial and ventricular pulse generator timing circuits being reset on sensing spontaneous ventricular activity.
Finally, U.S. Pat. No. 4,312,355 and assigned to the assignee of the present invention, discloses a pacemaker which, if required, may stimulate the atrium and/or ventricle on demand and which is able to maintain synchrony as the sensed atrial rate increases. A pacemaker of this type is capable of distinguishing between bradycardia and normal heart function and to provide atrial and/or ventricular pacing in the following modes: inhibited in the case where the atrium and ventricle beat at a sufficient rate; atrial demand in instances where the atrium is beating at an insufficient rate and must be stimulated whereas the ventricle properly follows; atrial synchronous when the atrium depolarizes at a sufficient rate but the ventricle does not follow within a prescribed A-V interval; and dual demand when neither the atrium nor the ventricle spontaeously depolarize at the desired rate.
All of the demand pacemakers of the types described above comprise ventricular or atrial and ventricular timing circuits which may be a simple oscillator of the early designs or the complex, programmable design described in U.S. Ser. No. 235,069 filed Feb. 17, 1981, in the name of L. Herpers, which itself employs digital timing circuits of the type disclosed, for example, in the, analog sense amplifier circuits of the type disclosed, for example, in my co-pending U.S. Ser. No. 957,825 filed Nov. 6, 1978, and analog output circuits of the type disclosed, for example, in the copending U.S. Ser. No. 957,826 filed Nov. 6, 1978 in the name of David L. Thompson, all assigned to the assignee of the present invention. The inputs of the respective sense amplifiers and the output capacitances of the output circuits are commonly coupled to the respective atrial or ventricular sense amplifiers and through pacing leads to the electrodes coupled to the patient's heart.
The lead, the output circuit presented to the lead, the heart and the electrode-tissue interface comprise a capacitive-resistive reactance into which the stimulating pulse (the discharge of the output capacitor) is delivered. During the delivery of a stimulation signal, the output capacitor is partially discharged and recharges during the interval between stimulation signals. At higher rates, particularly with long duration signals, the capacitor may not fully charge during that interval. This potential problem could be accommodated by reducing the time constant of the charge path of the output capacitor. However, in the context of a demand cardiac pacemaker it is desirable to have a high impedance in that path in that a high input impedance, as viewed from the heart, aids in sensing R waves. However, this higher impedance increases the time constant and, thus, the time of recharge. The sense amplifier of a demand cardiac pacemaker senses this activity and, thus, it would be desirable to speed up the recharge of the output capacitor to shorten the recovery time of the sense amplifier.
The prolonged saturation period is especially troublesome in atrial and ventricular pacemakers where it is desirable to be able to sense atrial and ventricular heart activity after both atrial and ventricular stimulation. Attempts have been made in ventricular demand pacemakers to shorten the recharge period as shown, for example, in U.S. Pat. Nos. 3,835,865 and 4,170,999 and in the circuit disclosed in the aforementioned co-pending U.S. Ser. No. 957,826. None of these circuits are adequate for the purpose of decreasing the objectionable saturation-recharge period to a desirable interval, e.g. 10 ms, while retaining desired characteristics of the output circuit.